1. Field of the Invention
The present invention relates to a semiconductor device, and a method for manufacturing the semiconductor device, specifically to the gate structure of an MOS transistor and the contact structure that contains gate wirings and LIC (local interconnect).
2. Background Art
Concurrent with the size reduction of semiconductor elements, the margin of the areas for forming contacts from the upper layer to the substrate also tends to decrease. Therefore, in order to prevent the occurrence of electrical short-circuiting from the element-isolating end to the substrate when a contact is out of an active region, methods for forming contacts known as a borderless contact structure or a self align contact structure (hereafter referred to as SAC structure) are positively adopted.
In the SAC structure, materials that have an etching selection ratio with a silicon oxide film often used as an interlayer insulating film are required. An example of such materials is silicon nitride film. Therefore silicon nitride films are often used in the vicinity of the gate electrodes of MOS transistors of an SAC structure.
FIG. 16 is a schematic sectional view that shows the configuration of an MOS transistor of an SAC structure. This MOS transistor is composed of a gate electrode 103 formed on a silicon semiconductor substrate 101 through a gate oxide film 102, and a pair of impurity diffusion layers 104 formed on the surface region of the silicon semiconductor substrate 101 at the both sides of the gate electrode 103. Here, the gate electrode 103 has a salicide structure consisting of a lower-layer polysilicon film 103a and an upper-layer silicide film 103b. Another silicide film 105 is formed on the surface layers of the impurity diffusion layers 104 by salicide forming.
A sidewall spacer 107 is formed on the sidewall of the gate electrode 103. A silicon nitride film 108 is formed so as to cover the surface of each of the sidewall spacer 107, the silicide film 105, and the silicide film 103b. The silicon nitride film 108 functions as the etching stopper film for inhibiting the contact hole from reaching the gate electrode 103 or the element-isolating end, even if the contact hole of the contact electrode 106 connected to the impurity diffusion layers 104 is misaligned.
In such a conventional MOS transistor of the SAC structure, the places where the silicon nitride film is used include 1) the sidewall spacer 107 of the transistor gate, and 2) the etching stopper film 108 for preventing junction leakage or wiring short-circuiting when the contact hole, LIC wirings, and the like are disposed in the vicinity of the element-isolating film or the gate electrode 103.
However, since the dielectric constant of the silicon nitride film is as high as twice the dielectric constant of the silicon oxide film or higher, the silicon nitride film increases the capacity between the gate electrode 103 and the impurity diffusion layers 104 such as the source/drain, the capacity between the gate electrodes 103 of the transistors adjacent to each other, the capacity between the gate electrode 103 and the contact electrode 106, and the capacity between the gate electrode 103 and the LIC wiring. Increase in capacity is particularly significant when the LIC wirings are formed in parallel along the transistor gate in order to lower resistance with the source or the drain.
FIG. 17 is a schematic diagram showing the gate overlapping capacity in each generation. It is seen from FIG. 17 that with each succeeding generation, the proportion of the capacity between the gate electrode and the contact (C2) increases in comparison with the capacity between the gate electrode and the diffused layer (C1). The reasons are decrease in pitch of gate electrodes or the distance between the gate electrode and the contact hole with down sizing, and increase in the proportion of the nitride film occupying the insulating film in the vicinity of the gate resulting in the elevation of effective dielectric constant. Increase in such parasitic capacity has interfered with advantages due to down sizing such as high speed and low power consumption.
Furthermore, as FIG. 18 shows, when the pitch of transistors is shortened, a problem of difficulty of forming silicide on the impurity diffusion layer 104 surrounded by the sidewall spacer 107 arises. This is because the formation of a refractory metal layer is difficult by methods such as sputtering, since the sidewall spacer 107 fills the space between gate electrodes 103. Also, a problem in which the stress of the nitride film inhibits the growth of silicide between gate electrodes arises. As a result, silicide resistance rises, inhibiting the high-speed operation of the device.
On the other hand, since a contact hole that connects a gate electrode and an impurity diffusion layer simultaneously (hereafter referred to as a shared contact) can reduce the memory cell size, it is used in memories that require high integration, such as SRAM cells. FIG. 19 is a schematic sectional view showing an example of an MOS transistor that has a shared contact electrode 114. Since a shared contact is characterized in a structure to connect a gate electrode at the upper portion of the electrode, it can connect a gate electrode and an impurity diffusion layer simultaneously without adding a special mask or an ion implantation step.
However, when a sidewall spacer 107 or an etching stopper film 108 as shown in FIGS. 16 and 18 is used, the portions of the sidewall spacer 107 and the etching stopper film 108 cannot contribute to connection to at least an impurity diffusion layer 105 as FIG. 19 shows. Therefore, the shared contact cannot be scaled to meet the requirements of down sizing, as FIG. 19 shows, the size reduction and high integration of memory cells cannot be achieved.
Furthermore, with decrease in the width Lg of the gate electrode 103 of a transistor, problems of increased wiring resistance and unstable resistance when silicide is formed arise.